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copyright ? cirrus logic, inc. 2005 (all rights reserved) http://www.cirrus.com cs5510/11/12/13 16-bit and 20-bit, 8-pin ? adc features z delta-sigma analog-to-digital converter ? linearity error: 0.0015% fs ? noise-free resolution: up to 17 bits z differential bipolar analog inputs z v ref input range from 250 mv to 5 v z 50/60 hz simultaneous rejection (cs5510/12) z 16 to 326 sps output word rate z on-chip oscillator (CS5511/13) z power supply configurations: ? v+ = 5 v, v- = 0 v ? multiple dual-supply arrangements z low power consumption ? normal mode, 2.5 mw ? sleep mode, 10 w z low-cost, compact, 8-pin package z lead-free device package options general description the cs5510/11/12/13 are low-cost, easy-to-use, ? an- alog-to-digital converters (adcs) which use charge- balance techniques to achieve 16-bit (cs5510/11) and 20-bit (cs5512/13) performance. the adcs are avail- able in a space-efficient, 8-pin soic package and are optimized for measuring signals in weigh scale, process control, and other industrial applications. to accommodate these applications, the adcs include a fourth-order ? modulator and a digital filter. when configured with an external master clock of 32.768 khz, the filter in the cs5510/12 provides better than 80 db of simultaneous 50 and 60 hz line rejection, and outputs conversion words at 53.5 sps. the CS5511/13 include an on-chip oscillator which e liminates the need for an ex- ternal clock source. low-power, flexible supply configurations, compact pi- nout, and ease of use make these products ideal solutions for cost-conscienc e and space-constrained applications. ordering in formation see page 23. v+ ain+ ain- vref clock gen. 1x ~0.8x differential 4th-order delta-sigma modulator digital filter control output sclk sdo logic oscillator (CS5511/13 only) v- (cs5510/12 only) cs aug ?05 ds337f3
cs5510/11/12/13 2 ds337f3 table of contents 1. characteristics and specifications ........................................................................ 4 analog characteristics ................................................................................................ 4 digital characteristics ................................................................................................. 5 dynamic characteristics .............................................................................................. 6 absolute maximum ratings ...... ................ ................ ................ ............. ............. ........... 6 switching characteristics - cs5510/12 ..................................................................... 7 switching characteristics - CS5511/13 ..................................................................... 8 2. general description ..................................................................................................... 10 2.1 analog input .............................................................................................................. ....... 10 2.1.1 analog input model ............................................................................................. 10 2.2 voltage reference input ..... ............................................................................................. 1 0 2.2.1 voltage reference input model ........... ................................................................ 11 2.3 power supply arrangements ........................................................................................... 11 2.3.1 digital logic levels ............................................................................................. 11 2.4 clock generator ........................................................................................................... .... 14 2.4.1 external clock source for cs5510/12 ................................................................ 14 2.4.2 internal oscillator for CS5511/13 ..... ................................................................... 14 2.5 performing conversions .................................................................................................. 15 2.5.1 reading conversions - cs5510/12 ..................................................................... 16 2.5.2 reading conversions - CS5511/13 ..................................................................... 16 2.5.3 output coding ..................................................................................................... 17 2.5.4 digital filter ......................................................................................................... 1 8 2.5.5 multiplexed applications ................... ................................................................... 19 2.6 digital off-chip system ca libration .................................................................................. 20 2.7 power consumption, sleep and reset ............................................................................ 20 2.8 pcb layout ................................................................................................................ ...... 20 3. pin descriptions .......................................................................................................... .... 21 4. specification definitions ............................................................................................. 22 5. ordering information ................................................................................................... 23 6. environmental, manufacturing, & hand ling information ............................ 23 7. revision history ......................................................................................................... .... 23 8. package dimensions ....................................................................................................... 2 4 contacting cirrus logic support for all product questions and inquiries cont act a cirrus logic sa les representative. to find the one nearest to you go to www.cirrus.com important notice cirrus logic, inc. and its subsidiaries (?cirrus?) believe that the information contained in this document is accurate and reli able. however, the information is subject to change without notice and is provided ?as is? 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cs5510/11/12/13 ds337f3 3 list of figures figure 1. sdo read timing cs55 10/12 (not to scale).................................................................. 9 figure 2. sdo read timing cs55 11/13 (not to scale).................................................................. 9 figure 3. input models for ain+ and ain- pins. . ........................................................................... 10 figure 4. cs5512/13 measured no ise-free bits vs. vref. ......................................................... 11 figure 5. input model for vref pin............................................................................................. .. 11 figure 6. cs5510/11/12/13 configured with a +5 .0 v analog supply. ......................................... 12 figure 7. cs5510/11/12/13 configured with 2.5 v analog supplies........................................... 12 figure 8. cs5510/11/12/13 configured with v+ = +3.3 v and v- = -1.7 v; or v+ = +3.0 v and v- = -2.0 v. .................................................................................... 13 figure 9. cs and sclk digital input levels. ................ ................................................................ 14 figure 10. sdo digital output levels. .......................................................................................... 14 figure 11. serial port output drive logic. ....... ............................................................................. 1 4 figure 12. external (cmos comp atible) clock source. ............... ................................................ 15 figure 13. using a microcontro ller as a clock source. ................................................................. 15 figure 14. typical linearity error for cs5510..... .......................................................................... 15 figure 15. typical linearity error for cs5512..... .......................................................................... 15 figure 16. data word timing fo r the cs5510............................................................................... 16 figure 17. data word timing fo r the CS5511............................................................................... 17 figure 18. data word timing fo r the cs5512............................................................................... 17 figure 19. data word timing fo r the cs5513............................................................................... 17 figure 20. digital filter response............................................................................................. .... 19 list of tables table 1. cs5512/13 output conversion data regi ster description (flags + 20 bits). ................. 18 table 2. cs5510/11 output conversion data regi ster description (flags + 16 bits). ................. 18 table 3. cs5510/11/12/13 output coding. ................................................................................... 18 table 4. digital filter response at 32.768 khz............................................................................. 19 table 5. device ordering inform ation ........................................................................................... 23
cs5510/11/12/13 4 ds337f3 1. characteristics and specifications analog characteristics (t a = 25 c; v+ = 5 v 5%; v- = 0 v; vref = 2.5 v (relative to v-); cs5510/12, sclk = 32.768 khz; CS5511/13, f osc = 64 khz 32 khz; owr (output word rate) = 53.5 sps for cs5510/12; owr = 107 sps 50% for CS5511/13) (see note 1.) notes: 1. specifications guaranteed by de sign, characterization, and/or test. 2. specification applies to the device only and does not include any effects by external parasitic thermocouples. 3. drift over specified temperature range after power-up at 25
cs5510/11/12/13 ds337f3 5 analog characteristics (continued) notes: 8. vref is referenced to v- and must be less than or equal to v+. 9. due to current through the cs pin, i v+ and i v- may not always be the same value. 10. all outputs unloaded. all in puts cmos levels (> (v+ - 0.6 v) or < (v- + 0.6 v)). 11. cs must be inactive (logic high) during sleep to meet this power specification. digital characteristics (t a = 25 c; v + ?digital logic levels? and figure 11 for more details. parameter min typ max unit voltage reference input range {(vref) - (v-)} (note 8) 0.250 2.5 (v+) - (v-) v input capacitance - 7 - pf cvf current - 6 - na power supplies supply voltages {(v+) - (v-)} 4.75 5 5.25 v dc power supply currents (note 9) i v+ cs5510 CS5511 cs5512 cs5513 i v- cs5510 CS5511 cs5512 cs5513 - - - - - - - - 275 290 360 385 275 290 360 385 360 380 470 500 360 380 470 500 a a a a a a a a power consumption (note 10) cs5510 CS5511 cs5512 cs5513 sleep (note 11) - - - - - 1.4 1.5 1.8 1.9 10 1.9 2.0 2.5 2.7 - mw mw mw mw w power supply rejection dc positive supply dc negative supply - - 85 85 - - db db parameter symbol min typ max unit high-level input voltage: cs and sclk v ih v+ - 0.45 - - v low-level input voltage: (note 13) cs sclk cs low v il - - - - v l1 v l1 v v input current: (note 14) cs i cs - -1.0ma high-level output voltage: sdo, i source = 5.0ma v oh (v+) - 0.6 - - v low-level output voltage: (note 14) sdo, i sink = 1.0ma v ol --( cs low ) + 0.6 v input leakage current sclk i in - 0.015 10 a 3-state leakage current sclk i oz -- 10a
cs5510/11/12/13 6 ds337f3 dynamic characteristics absolute maximum ratings (v- = 0 v) (see note 15.) notes: 15. all voltages with respect to v-. 16. v+ and v- must satisfy 0.0v
cs5510/11/12/13 ds337f3 7 switching characteris tics - cs5510/12 (t a = 25 c; v+ = 5 v 5%; v- = 0 v; input levels: logic 0 = 0 v, logic 1 = v+; c l = 50 pf) notes: 20. device parameters are specified with 32.768 khz clock; however, clocks up to 130 khz (cs5510) or 200 khz (cs5512) can be used for increased through put. higher clock rates will result in degraded linearity specifications, as shown in figures 14 and 15. 21. specified using 10% and 90% points on waveform of interest. output loaded with 50 pf. 22. on the cs5510/12, the serial clock input (sclk) pr ovides the master clock to operate the converter as well as the serial data clock used to read conver sion data. if sclk is held high (logic 1) for t slp or longer, the cs5510/12 enters sleep. to exit from sle ep mode, sclk must be held low (logic 0) for t wake or longer. parameter symbol min typ max unit master clock timing master clock frequency (cs5510) (note 20) sclk 10 32.768 130 khz master clock frequency (cs5512) (note 20) sclk 10 32.768 200 khz master clock duty cycle 40 - 60 % rise times (note 21) csb sclk sdo t rise - - - - - 50 1.0 10 - s s ns fall times (note 21) csb sclk sdo t fall - - - - - 50 1.0 10 - s s ns serial port timing serial clock frequency (cs55 10) (note 22) sclk 10 32.768 130 khz serial clock frequency (cs55 12) (note 22) sclk 10 32.768 200 khz sclk high to enter sleep (note 22) t slp 200 - 2000 s sclk low to exit sleep (note 22) t wake 10 - - s serial clock pulse width high pulse width low t 1 t 2 2 2 - - 60 60 s s sdo read timing cs to data valid t 3 --150ns sclk falling to new data bit t 4 --150ns cs rising to sdo hi-z t 5 --150ns cs falling to sclk rising t 11 200 - - ns
cs5510/11/12/13 8 ds337f3 switching characteris tics - CS5511/13 (t a = 25 c; v+ = 5 v 5%; v- = 0 v; input levels: logic 0 = 0 v, logic 1 = v+; c l = 50 pf) notes: 23. the internal oscillator in the CS5511/13 provides the master clock fo r performing conversions. data is retrieved from the serial port using the sclk input pin. 24. the minimum sclk rate for the CS5511/13 assumes that sclk is logic 0 when idle. when data is being read from the adc, sclk must be burst at a mi nimum rate of 10 khz and with a minimum of a 10 percent duty cycle. rates slower than this can potenti ally put the adc into sleep as the sleep mode is entered after sclk is logic 1 for t slp time. 25. on the CS5511/13, the serial clock (sclk) is used to transfer data from the CS5511/13. if sclk is held high (logic 1) for t slp or longer, the CS5511/13 enters sleep mode . to exit from sleep mode, sclk must be held low (logic 0) for t wake or longer. 26. specified using 10% and 90% points on waveform of interest. output loaded with 50 pf. parameter symbol min typ max unit internal oscillator timing internal oscillator frequency (note 23) f osc 32 64 100 khz internal oscillator drift ov er temperature - - -0.02 - %/c serial port timing serial clock frequency (note 24) sclk - - 2 mhz sclk high to enter sleep (notes 24 and 25) t slp 200 - 2000 s sclk low to exit sleep (notes 24 and 25) t wake 10 - - s rise times (note 26) csb sclk sdo t rise - - - - - 50 1.0 10 - s s ns fall times (note 26) csb sclk sdo t fall - - - - - 50 1.0 10 - s s ns serial clock pulse width high pulse width low t 6 t 7 200 200 - - - - ns ns sdo read timing cs to data valid t 8 --150ns sclk falling to new data bit t 9 --150ns cs rising to sdo hi-z t 10 --150ns cs falling to sclk rising t 11 200 - - ns
cs5510/11/12/13 ds337f3 9 msb msb-1 lsb t3 t5 t4 t1 t2 t11 sclk sdo cs figure 1. sdo read timing cs5510/12 (not to scale). figure 2. sdo read timing CS5511/13 (not to scale). msb msb-1 lsb t8 t10 t9 t6 t7 t11 sdo cs sclk
cs5510/11/12/13 10 ds337f3 2. general description the cs5510/11/12/13 are low-cost, easy-to-use, ? analog-to-digital converters (adcs) which use charge balance techniques to achieve 16-bit (cs5510/11) and 20-bit (cs5512/13) perfor- mance. the adcs are available in a space-effi- cient, 8-pin, soic package and are optimized for measuring signals in weigh scale, process control, and other industrial applications. to accommodate these applications, the adcs in- clude a fourth-order ? modulator and a digital fil- ter. when configured with an external master clock of 32.768 khz, the filter in the cs5510/12 provides better than 80 db of simultaneous 50 and 60 hz line rejection, and outputs conversion words at 53.5 sps. the CS5511/13 include an on-chip oscil- lator which eliminates the need for an external clock source. the cs5510/11/12/13 adcs are designed to oper- ate from a single +5 v supply or a variety dual-sup- ply configurations and are optimized to digitize bipolar signals in industrial applications. to achieve low cost, the cs5510/11/12/13 family of converters have no on-chip calibration features. the cs5510/11/12/13 offer very low offset drift, low gain drift, and excellent linearity. 2.1 analog input the cs5510/11/12/13 provides a differential input span of approximately (0.80 0.08) times the dif- ferential voltage reference (vref - v-). this trans- lates to typically 4.0 v fully differential when the reference voltage between vref and v- is 5 v, and typically 2.0 v fully differential at 2.5 v. note: when a smaller reference voltage is used, the resulting code width s are smaller. since the output codes exhibit more changing codes for a fixed amount of noise, the converter appears noisier. 2.1.1 analog input model figure 3 illustrates the input model for the ain pins. the model includes a coarse/fine charge buffer which reduces the dynamic current de- mands from the signal s ource. the buffer is de- signed to accommodate rail-to-rail (common-mode plus signal) input voltages . typical cvf (sampling) current is about 10 na. application note 30, ?switched-capacitor a/d input structures? , details various input architectures. 2.2 voltage reference input the voltage between the vref and v- pins of the converter determines the voltage reference for the converter. this voltage can be as low as 250 mv, or as great as (v+) - (v-). the vref pin can be connected directly to the v+ pin. this will establish a voltage reference equal to (v+) - (v-) for the con- verter. the effective resolution of the part (noise- free bits for a single sample with no averaging) will vary with vref. figure 4 shows how the vref voltage affects the noise-free resolution of the ain = fv c os n c = 1 2 p f figure 3. input models for ain+ and ain- pins.
cs5510/11/12/13 ds337f3 11 cs5512/13. the cs5510/11 follow the same curve, but are limited to 16 bits of resolution. note that the reference voltage should not be estab- lished prior to having the supply voltages on the v+ and v- pins. 2.2.1 voltage refe rence input model figure 5 illustrates the input model for the vref pin. it includes a coarse/fine charge buffer which reduces the dynamic current demand of the exter- nal reference. typical cvf (sampling) current is about 6 na (see figure 5). the nominal input span of the converter is defined to be a bipolar span equal to (vref - v-)*(0.80 0.08). 2.3 power supply arrangements the cs5510/11/12/13 are designed to operate from single or dual supplies. figure 6 illustrates the cs5510/11/12/13 connected with a single +5 v supply to measure differential inputs relative to a common mode of 2.5 v. figure 7 illustrates the cs5510/11/12/13 connected with 2.5 v analog supplies to measure ground-referenced, bipolar signals. it is not necessary that the dual supples on the adcs be balanced, however, they must sum to five volts. figure 8 illustrates the adcs configured with v+ = +3.3 v and v- = -1.7 v, accommodating a +3.3 v digital supply. 2.3.1 digital logic levels the many power supply conf igurations available in the cs5510/11/12/13 allow for a wide range of dig- ital logic levels. the logic-high input and output lev- els are determined by the v+ pin. the logic-low output on sdo is referenced to and driven by the current logic-low voltage on cs . since the cs5510/11/12/13 do not include a dedicated 13 14 15 16 17 00.511.522.533.544.55 vref (v) effective bits figure 4. cs5512/13 measured noise-free bits vs. vref. vref c = 7pf 2 = fv c os n f = 32.768 khz coarse fine figure 5. input model for vref pin.
cs5510/11/12/13 12 ds337f3 v+ vref ain+ sclk sdo cs5510/11/12/13 cs +5.0 v supply 1 2 6 8 4 clock source serial data interface ain- 3 v- 7 0.1 figure 6. cs5510/11/12/13 configured with a +5.0 v analog supply. v+ vref ain+ sclk sdo cs5510/11/12/13 cs +2.5 v supply 1 2 6 8 4 clock source serial data interface ain- 3 v- 7 + - 0.1 figure 7. cs5510/11/12/13 configured with 2.5 v analog supplies.
cs5510/11/12/13 ds337f3 13 v+ vref ain+ sclk sdo cs5510/11/12/13 cs +3.3 v/+3.0v supply 1 2 6 8 4 clock source serial data interface ain- 3 v- 7 + - 0.1 figure 8. cs5510/11/12/13 configured with v+ = +3.3 v and v- = -1.7 v; or v+ = +3.0 v and v- = -2.0 v.
cs5510/11/12/13 14 ds337f3 ground pin, cs low defines the logic-low level for the digital interface. figures 9 and 10 illustrate the threshold levels of the cs5510/11/12/13 serial in- terface (cs , sclk, and sdo). to accommodate opto-isolators, the sclk input is designed with a schmitt-trigger to allow an opto- isolator with slower rise and fall times to directly drive the pin. additionally, sdo is capable of sink- ing up to 1 ma or sourcing up to 5 ma to directly drive an opto-isolator led. sdo will have less than a 600 mv loss in the drive voltage when sinking or sourcing its current. as shown in figure 11, the cs signal provides the sink current path for the sdo pin when its voltage is low (i.e. the voltage speci- fied for sdo is relative to cs low .). 2.4 clock generator the cs5510/12 and CS5511/13 provide distinct modes for generating the master clock for the adcs. the cs5510/12 uses the sclk input pin as its operating clock. the CS5511/13 has an on-chip oscillator that provides its master clock. the sclk pin on the CS5511/13 is used only to read data and to put the part into sleep mode. 2.4.1 external clock source for cs5510/12 the user must provide an external (cmos com- patible) clock to the cs5510/12. the clock is input to sclk where it is then divided down to provide the master clock for the adc. the output word rate (owr) for the cs5510/12 is derived from the sclk, and is equal to sclk/612. figure 12 illus- trates an external 32.768-khz, cmos-compatible clock oscillator that a user might consider. another clock generation option is to use a micro- controller. some microcontrollers have dedicated timer/counter circuitry wh ich can generate a clock signal on an output pin wi th no software overhead. such a microcontroller circuit is shown in figure 13. note that the cs5510 can operate with an exter- nal, cmos-compatible cl ock at frequencies up to 130 khz, and the cs5512 can operate with an ex- ternal clock of up to 200 khz with a maximum 22 ns of jitter. linearity performance is degraded slightly with higher clock speeds, as shown in figures 14 and 15. the noise performance of the parts, however, is not affected by higher clock speeds. 2.4.2 internal oscillator for CS5511/13 the CS5511/13 includes an on-chip oscillator. this oscillator provides the master clock for the CS5511/13 and oscillates at 64 khz 32 khz. the figure 9. cs and sclk digital input levels. v+ v- v v=0.5( -v-)+0.6 v- ih il low - 0.45v v+ = = cs v+ v+ v+ v- v=v+-0.6v v=cs +0.6v oh ol low v il cs low figure 10. sdo digital output levels. v+ output drive logic 5ma 1ma sdo (from sdo control logic) cs (to cs control logic) max source max sink figure 11. serial port output drive logic.
cs5510/11/12/13 ds337f3 15 output word rate (owr) for the CS5511/13 is de- rived from the internal oscillator, and is equal to f osc /612. due to the part-to-part variances in the oscillator frequency, the owr of the CS5511/13 can vary between 53 sps and 159 sps. 2.5 performing conversions after power and a clock source are established to the cs5510/11/12/13, the adcs begin performing conversions. the three sections that follow explain how to read conversion data from each adc, and decode the conversion word into the respective flag and data bits. keep in mind that in the cs5510/12, sclk provides the external clock source for the converter. data is clocked from the cs5510/12 at the rate set by the external clock source (typically 32.768 khz). the CS5511/13 pro- vides an on-chip oscillator for the master clock. in the CS5511/13, sclk is asynchronous to the on- chip oscillator and can be clocked at a rate up to 2mhz. vd+ = 2.5 v to 5.25 v to sclk fairchild nc7su04 or 1/6 74hcu04 22 pf 47 pf 32.768 khz 49.9 k ? ? figure 12. external (cmos compatible) clock counter/timer sclk sdo cs cs5510/12 c figure 13. using a microcontroller as a clock 0 0.0005 0.001 0.0015 0.002 0.0025 0.003 0.0035 0.004 10 30 50 70 90 110 130 sclk (khz) linearity error (%fs) owr = sclk 612 figure 14. typical linearity error for cs5510. 0 0.0005 0.001 0.0015 0.002 0.0025 0.003 0 20 40 60 80 100 120 140 160 180 200 sclk (khz) linearity error (%fs) owr = sclk 612 figure 15. typical linearity error for cs5512.
cs5510/11/12/13 16 ds337f3 2.5.1 reading conversions - cs5510/12 after power-up, the cs5510/12 will begin convert- ing once a clock source is applied to the sclk pin. when a conversion has completed, and there is new data in the output register, the sdo line will fall to a logic-low level if cs is also at a logic-low state (sdo will always be high-impedance when cs is high). if cs is low at the end of the conver- sion cycle, sdo will fall on the rising edge of an sclk. after sclk falls, the next sclk cycle (high, then low) will begin clocking out the data. the first data bit therefore, is 1- ? sclk cycles wide. twen- ty-four sclk cycles (after the initial high-low tran- sition) are needed to retrieve the conversion word from the device (see figures 16 and 17). the data bits can be read on the rising edge of sclk, and the next data bit is output to sdo on the falling edge of sclk. once the entire data word has been read, sdo will return to a logic-high state until there is a new conversion word available. if cs is at a logic-high at the end of the conversion cycle, the data will not be shifted out of the part until cs is brought to a logic-low state during the next con- version cycle. if a new co nversion becomes avail- able while the current data is being read, the data register will not be updated, and the new conver- sion word will be lost. the user need not read every conversion. if the user chooses not to read a con- version, cs should remain at a logic-high state for the duration of the conversion cycle. note that if cs goes to a logic-high state during a read, the current conversion data will be lost and replaced by a new conversion word when the new conver- sion data is available. 2.5.2 reading conversions - CS5511/13 after power-up, the CS5511/13 begins converting and updating the output register. when there is new data in the output register (at the end of a con- version cycle) the sdo line will fall to a logic-low level if cs is also at a logic-low state (sdo will al- ways be high-impedance when cs is high). twen- ty-four sclk cycles are needed to retrieve the conversion word from the device (see figures 18 and 19). the data bits can be read on the rising edge of sclk, and the next data bit is output to sdo on the falling edge of sclk. once the entire data word has been read, sdo will return to a log- ic-high state until there is a new conversion word available. if new conver sions become available while the current data is being read, the data regis- ter will not be updated, and the new conversions will be lost. the user need not read every conver- sion. if the user chooses not to read a conversion after sdo falls, sdo will rise seventeen oscillator clock cycles (of the internal oscillator) before the next conversion word is available and then fall again to signal that the conversion is complete. note that if a conversion word is not read before the next conversion word is ready, or if cs goes to a logic-high state during a read, the current conver- sion data will be lost and replaced by a new con- version word when the new conversion data is available. sdo sclk data time 24 sclks msb lsb cs 0 of od 0 00 0 0 0 0 figure 16. data word timing for the cs5510.
cs5510/11/12/13 ds337f3 17 2.5.3 output coding as shown in tables 1 and 2, the cs5510/11/12/13 present output conversions as 24-bit conversion words. the first bit of the conversion word indi- cates that a conversion is done through sdo fall- ing from a logic high to a logic low level. the first and the fourth bits output will always be zero. the second and third bits are error flags, representing an overflow or oscillation condition. in the cs5510/11, there are four more bits of zero, and the remaining 16 bits are the conversion data, out- put msb first (table 2). in the cs5512/13, the final 20 bits are the conversion data, which is output msb first (table 1). bits d22-d21 are the two flag bits. the of (over- range flag) bit is set to a logic 1 any time the input signal is more positive than positive full scale, or more negative than negative full scale. it is cleared back to logic 0 whenever a conversion word occurs which is not overranged. the od (osc illation de- tect) bit is set to a logic 1 any time that an oscillatory condition is detected in the modulator. this does not occur under normal operating conditions, but may occur whenever the input to the converter is ex- sdo sclk d ata tim e 24 sclks msb lsb cs 0 of od 0 0000 0 0 figure 17. data word timing for the CS5511. sdo sclk d ata tim e 24 sclks msb lsb cs 0 of od 0 0 0 figure 18. data word timing for the cs5512. sdo sclk data time 24 sclks msb lsb cs 0 of od 0 0 0 figure 19. data word timing for the cs5513.
cs5510/11/12/13 18 ds337f3 cessively overranged. if the od bit is set, the con- version data bits can be completely erroneous. the od flag bit will be cleared to logic 0 four output words after the modulator becomes stable again. the od flag can occur independent of of with a spike on the input. both flag bits should be tested if any overrange condition occurs. table 3 illustrates the output coding for the cs5510/11/12/13. conversions are output as two's complement values representing bipolar in- put signals. 2.5.4 digital filter the cs5510/11/12/13 have a modified sinc 4 digi- tal filter that provides clk/612 hz conversion rates (clk represents sclk for the cs5510/12 and the internal oscillator for the CS5511/13). the filters are optimized to yield better than 80 db rejection between 47 hz to 63 hz (i.e. 80 db minimum rejec- tion for both 50 hz and 60 hz) when the master clock is 32.768 khz. the filter has a response as shown in figure 20. table 4 shows the filter re- sponse for frequencies from 38 hz to 71 hz. note that the response of the CS5511/13 will be similar, but the frequencies scale wi th the on-chip oscilla- tor?s frequency, which can be from 32 khz to 96 khz (i.e. conversion rates can vary between 53 sps to 159 sps). further note that after initial power up, or after returning from sleep mode, the filter requires four conversion cycles to produce a d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 0ofod0msb1817 1615 14 13 12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 11109876 5 4 3 2 1lsb table 1. cs5512/13 output conversion data register description (flags + 20 bits). d23 d22 d21 d20 d19 d18 d17 d16 d15 d14 d13 d12 0ofod0 0 0 0 0msb14 13 12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 11109876 5 4 3 2 1lsb table 2. cs5510/11 output conversion data register description (flags + 16 bits). note: vfs in the table equals the voltage between ain+ and ain-. see te xt about error flags under overrange conditions. table 3. cs5510/11/12/13 output coding. bipolar input voltage two's complement (20-bit) two's complement (16-bit) >(vfs-1.5 lsb) 7ffff 7fff vfs-1.5 lsb 7ffff ----- 7fffe 7fff ----- 7ffe -0.5 lsb 00000 ----- fffff 0000 ----- ffff -vfs+0.5 lsb 80001 ----- 80000 8001 ----- 8000
cs5510/11/12/13 ds337f3 19 valid conversion due to the modified sinc 4 filter characteristics. 2.5.5 multiplexed applications the settling performance of the cs5510/11/12/13 in multiplexed applications is determined by the sinc 4 filter. to settle, a step input requires 4 full conversion cycles after the analog input has switched. in this case, the throughput is reduced by a factor of four as the first three conversions af- ter the step is applied will not be fully settled. if the application does not require the maximum throughput possible from the adc, the multiplexer can be switched at any time. in this case, the sys- tem must wait for at least five conversion cycles for a fully-settled result from the adc. if maximum throughput is required in a multiplexed application, the multiplexer must be switched at the correct time during the data collection process. for maximum throughput with the cs5510/12, switch- ing of a multiplexer should occur 595 sclk cycles after sdo falls. for maximum throughput with the CS5511/13, switching of a multiplexer should oc- cur on the rising edge of sdo during a conversion in which the data word is not read. the conversion data that is immediately available when sdo falls again is valid, and represents the analog input from the previous multiplexer setting. the next three conversions from the part will be unsettled values, and the fourth conversion will represent a fully-set- tled result from the new multiplexer setting. the multiplexer should be switched again at the appro- -140 -120 -100 -80 -60 -40 -20 0 02040 60 80 100 120 frequency (hz) magnitude (db) 47 hz 63 hz cs5510/12 sclk = 32.768 khz figure 20. digital filter response. frequency (hz) rejection (db) frequency (hz) rejection (db) frequency (hz) rejection (db) frequency (hz) rejection (db) 38 37 47 84 56 91 65 73 39 39 48 92 57 109 66 69 40 42 49 88 58 94 67 66 41 46 50 92 59 89 68 64 42 49 51 105 60 88 69 63 43 54 52 89 61 92 70 61 44 58 53 86 62 104 71 60 45 64 54 85 63 84 - - 46 72 55 87 64 77 - - table 4. digital filter response at 32.768 khz.
cs5510/11/12/13 20 ds337f3 priate time during the third conversion cycle to en- sure the maximum possible throughput. 2.6 digital off-chip system calibration the cs5510/11/12/13 exhibit excellent linearity with low offset and gain drift, without the need for calibration. if precision voltage measurements are required by the system, however, software-based offset and gain calibration can be performed by the system. to perform a software offset calibration, the ?zero- point? of the system should be established by ap- plying an input to the system equal to zero. then, the user can obtain a conversion and store it in memory as the system?s zero point (zp). this num- ber can then be used as the zero point for any sub- sequent conversion words. in the 20-bit devices (cs5512 and cs5513), multiple conversions can be averaged to arrive at a more accurate offset val- ue. in the 16-bit devices (cs5510 and CS5511), averaging may not be m eaningful, because the noise will be below the size of one lsb when using nominal voltages for vref (2.5 v). a software gain calibration can be performed by bringing the system to a known calibration voltage value (vcal) and acquiring a conversion (note that vcal should be low enough to compensate for the possible gain error of the adc). multiple conver- sions can be averaged at this point to improve the accuracy of the calibration. the code obtained from this conversion is the real value (cr) of the calibration voltage input, and will differ from the ideal value. the ideal val ue for this conversion (ci) will be equivalent to: 0x7fff*vcal/(0.80*vref) for the cs5510/11, and 0x7ffff*vcal/(0.80*vref) for the cs5512/13. the gain error (ge) is equal to: (cr - zp)/ci. to correct for both offset and gain error in subsequent conversions, subtract the offset error, and then divide by the gain error. 2.7 power consumption, sleep and reset the cs5510/11/12/13 accommodates two power modes: normal and sleep . the normal mode is the default mode and is entered after power is estab- lished to the adc. in normal mode, the adcs typ- ically consumes 2.5 mw. sleep is entered when the user leaves sclk high for at least 200 s. the adcs are guaranteed to be in sleep after sclk is high (logic 1) for 2 ms. the sleep mode reduces the consumed power to less than 10 w when cs is high (logic 1). if cs is low (logic 0) at this time, the sdo drive logic will still be active, and the con- sumed sleep power will be greater. to exit sleep and return to normal mode, the user must return sclk low for at least 10 s. after a sleep is exited, the adcs reset all their internal logic, including their digital filters, and begin performing conver- sions. since the filters are reset, the first three con- version after returning to normal mode will not be fully settled. 2.8 pcb layout the cs5510/11/12/13 should be placed entirely over the analog ground. place the analog-digital plane split immediately adjacent to the digital pins of the chip.
cs5510/11/12/13 ds337f3 21 3. pin descriptions control pins and serial data i/o cs - chip select, pin 4 cs is a dual function pin, which det ermines the state of sdo, as well as the digital logic-low output level. when cs is low, sdo will be active. when high, th e sdo pin will output a high-impedance state. the logic-low level of sdo will match the active-low voltage on cs . sdo - serial data output, pin 8 sdo is the serial data output. it will output a high-imp edance state if cs = 1. the logic-low level of sdo will match the active-low voltage on cs . sclk - serial clock input, pin 5 sclk is the serial bit-clock which controls the shifti ng of data from the adcs. this input goes through a schmitt trigger to allow for slow ri se and fall time signals. if held high, the device will enter sleep mode. in the cs5510/12, this input is also used as a mast er clock source which determines conversion speeds and throughput. in the CS5511/13, sclk is only used to read the conversion data and put the part in sleep mode. measurement and reference inputs ain+, ain- - differential analog input, pins 2, 3 differential input pins into the device vref - voltage reference input, pin 1 input voltage which establishes the voltage referenc e, with respect to v-, for the on-chip modulator power supply connections v+ - positive power, pin 6 positive supply voltage v- - negative supply, pin 7 negative supply voltage 1 2 3 45 6 7 8 sdo v- v+ sclk cs ain- ain+ vref
cs5510/11/12/13 22 ds337f3 4. specification definitions linearity error the deviation of a code from a straight line which connects the two end points of the a/d converter transfer function. one end point is located 1/2 lsb below the first code transition and the other end point is located 1/2 lsb beyond the code transiti on to all ones. units in percent of full-scale. differential nonlinearity the deviation of a code's width from the ideal width. units in lsbs. full scale error the deviation of the last code transition from the ideal [{(vref) - (v-)} - 3/2 lsb]. units are in lsbs. bipolar offset the deviation of the mid-scale transition (111...111 to 000...000) from the ideal (1/2 lsb below the voltage on the ain- pin). units are in lsbs.lk
cs5510/11/12/13 ds337f3 23 5. ordering information 6. environmental, manufacturi ng, & handling information * msl (moisture sensitivity level) as specified by ipc/jedec j-std-020. 7. revision history device number oscillator resolution linear ity error (max) temperature range package cs5510-as external 16 bits 0.003% -40 c to +85 c8-pin soic cs5510-asz (lead free) CS5511-as internal CS5511-asz (lead free) cs5512-bs external 20 bits 0.0015% cs5512-bsz (lead free) cs5513-bs internal cs5513-bsz (lead free) model number peak reflow temp msl rating* max floor life cs5510-as 240 c 2 365 days cs5510-asz (lead free) 260 c 3 7 days CS5511-as 240 c 2 365 days CS5511-asz (lead free) 260 c 3 7 days cs5512-bs 240 c 2 365 days cs5512-bsz (lead free) 260 c 3 7 days cs5513-bs 240 c 2 365 days cs5513-bsz (lead free) 260 c 3 7 days revision date changes f2 mar 2005 added lead-free device ordering information. f3 aug 2005 updated lead-free device ordering information. added msl data.
cs5510/11/12/13 24 ds337f3 8. package dimensions inches millimeters dim min nom max min nom max a 0.076 0.080 0.084 1.93 2.03 2.13 a1 0.004 0.007 0.010 0.10 0.175 0.25 b 0.013 0.016 0.020 0.33 0.406 0.51 c 0.006 0.008 0.010 0.15 0.20 0.25 d 0.206 0.208 0.210 5.23 5.28 5.33 e 0.204 0.208 0.212 5.18 5.28 5.38 e 0.040 0.050 0.060 1.02 1.27 1.52 h 0.302 0.310 0.318 7.67 7.88 8.08 l 0.019 0.025 0.030 0.48 0.64 0.76

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